Camera Control

This section describes how to run the camera control demo script for the Sony FCB-EV9520L on the AstrOptix Orin Super Carrier Board.

Download the Control Script

In Host PC, download the control_ev9520l.py script file from the download link below and copy it to the AstrOptix Orin Super Carrier Board:

Download Link: control_ev9520l.py

Note:

If file is not able to download, go through Full Script section below.

Install Dependencies on AstrOptix Board

Before running the script, install the required Python libraries on the AstrOptix Board. Open a terminal and run the following commands:

Update Package List

sudo apt update

Install pip3

sudo apt install python3-pip

Dependency 1 — smbus2

pip3 install smbus2    # for i2c communication

Dependency 2 — pyserial

pip3 install pyserial    # for serial communication

Script Overview

The control script initializes the UART bridge over I²C, configures the UART channel at 9600 baud (8N1 format), and sends VISCA command frames to the camera — for example, a ZoomIn / ZoomOut pair with a delay between them.

Function	Description
I²C Initialization	Opens the I²C bus, connects to the UART bridge chip
UART Configuration	Configures the UART channel — 9600 baud, 8N1 format, FIFO enabled
TX Ready Check	Polls the Line Status Register (LSR) until the Transmit Holding Register (THR) is empty and ready
Command Frame	Sends a 6-byte VISCA command frame to the camera via UART

Full Script

import smbus2
import time
 
bus = smbus2.SMBus(9)
I2C_ADDR = 0x48  # A0=A1=0
 
def write_reg(subaddr, data, channel=0):
    bus.write_byte_data(I2C_ADDR, (subaddr << 3) | 0x00, data)
 
def read_reg(subaddr, channel=0):
    return bus.read_byte_data(I2C_ADDR, (subaddr << 3) | 0x00)
 
# Initialize UART
write_reg(0x03, 0x80)  # LCR: Enable divisor
write_reg(0x00, 0x5B)  # DLL: 91 (9600 baud, 14.7456MHz crystal)
write_reg(0x01, 0x00)  # DLH: 0
write_reg(0x03, 0x03)  # LCR: 8N1
write_reg(0x02, 0x01)  # FCR: Enable FIFO
write_reg(0x01, 0x03)  # IER: Enable TX holding
 
# Verify LSR (Line Status Register) for TX ready
while not (read_reg(0x05) & 0x20):  # Check THR empty
    time.sleep(0.01)
 
# Send VISCA ZoomIn / ZoomOut command frames
data = [0x81, 0x01, 0x04, 0x07, 0x27, 0xFF]
data1 = [0x81, 0x01, 0x04, 0x07, 0x37, 0xFF]
for b in data:
    write_reg(0x00, b)
    time.sleep(0.01)
time.sleep(4)
for b in data1:
    write_reg(0x00, b)
    time.sleep(0.01)