NXP i.MX93 Series
The i.MX93 adopts the modern Cadence CSI2RX architecture, moving away from the legacy bridge design. Our drivers leverage the mainline cdns-csi2rx driver for robust, future-proof integration.
NXP i.MX93
The i.MX93 uses the Cadence CSI2RX + D-PHY RX IP, providing two 4-lane CSI-2 receivers (1.5 Gbps per lane). Unlike i.MX8M, it does not use the legacy CSI bridge—its CSI block is fully mainline-supported via the cdns-csi2rx driver.
- Cadence CSI2RX + D-PHY RX IP
- Two 4-lane CSI-2 receivers
- Mainline cdns-csi2rx driver
- Strong mainline kernel support (6.1+)
Device-tree nodes define data-lanes, link-frequency (typically 720–800 MHz), virtual-channel mapping, and DMA parameters. Power/reset use standard regulators and GPIO frameworks. Supported formats include RAW8–14, YUV422, and virtual-channel capture. Kernel support is strong in mainline (6.1+), enabling clean integration with Yocto/Buildroot. Flashing via U-Boot on EVK or custom modules. The i.MX93 is preferred when long-term mainline stability and modern CSI2RX architecture are required.
