NXP i.MX8M Series – MIPI CSI-2 Camera Drivers
The i.MX8M family (Plus, Mini, Nano) shares a common MIPI CSI-2 bridge architecture (imx8m-mipi-csi2) and media-controller framework. Whether using the dual-ISP power of the i.MX8M Plus or the cost-effective Mini/Nano, our drivers ensure seamless sensor integration, V4L2 compliance, and production-ready stability.
NXP i.MX8M Plus
The i.MX8M Plus integrates two independent 4-lane MIPI CSI-2 receivers, each supporting up to 1.5 Gbps per lane. Both receivers feed into the on-chip Image Signal Processor (ISI) that provides scaling, color conversion, dewarp, and basic processing.
- Two independent 4-lane MIPI CSI-2
- On-chip Image Signal Processor (ISI)
- Supports dual 4-lane 4K30 or dual 1080p60
- NXP BSP (L5.15/L6.1) or Mainline support
The driver architecture uses the standard imx8m-mipi-csi2.c receiver + CSI bridge design. Sensor drivers register as V4L2 async sub-devices under drivers/media/i2c/. Device-tree nodes (mipi_csi_0, mipi_csi_1) define data-lanes, clock-lane, link-frequency (typically 600–800 MHz), settle parameters, and pixel clock constraints. Power sequencing uses the standard regulator framework for AVDD/DVDD/IOVDD and sensor reset GPIOs. The hardware supports RAW8–14 Bayer, YUV422, and passthrough modes into the ISI. Bandwidth realistically supports dual 4-lane 4K30 or dual 1080p60 depending on the sensor and pipeline load (not 4K60). Builds follow NXP BSP (L5.15/L6.1) or mainline 6.6+ via Yocto/Buildroot/Debian. Flashing is via U-Boot on EVK, Toradex Verdin, Variscite, Compulab, and custom carriers.
NXP i.MX8M Mini
The i.MX8M Mini provides one 4-lane MIPI CSI-2 interface at up to 1.5 Gbps per lane. It shares the same CSI bridge and imx8m-mipi-csi2.c driver core as the Plus/Nano/MQ.
- One 4-lane MIPI CSI-2 interface
- Shared driver core with Plus/Nano
- Supports RAW10/12 and YUV passthrough
- Ideal for industrial vision platforms
Operation is the same: V4L2 async sub-devices, media-controller routing through mipi_csi_0, device-tree definitions for data-lanes, link-frequencies (400–800 MHz), and hs-settle. Power sequencing uses regulator + reset-gpios. Formats include RAW10/12 and YUV passthrough to the lightweight ISI block (reduced vs Plus). Because the CSI receiver is shared across all i.MX8M SoCs, a driver validated on i.MX8M Plus runs unchanged on Mini (only clock-tree/pooling differs). Build and flashing follow NXP BSP L5.15/L6.1 or mainline. Widely deployed on Verdin iMX8M Mini, Kontron, Boundary Devices, and industrial vision platforms. Suitable for single 4K30 / dual 1080p30 (not 1080p60 across two sensors due to internal ISI limits).
NXP i.MX8M Nano
The i.MX8M Nano retains the same single 4-lane CSI-2 receiver (up to 1.5 Gbps/lane) and identical imx8m-mipi-csi2 driver as Mini and Plus. The media-controller pipeline, lane mapping, power sequencing, link-freq, settle-time properties are entirely shared.
- Single 4-lane CSI-2 receiver
- Identical driver to Mini/Plus
- Low-power HMIs and compact cameras
- TechNexion, Variscite module support
The major differences vs Mini/Plus are in CPU/GPU capability and a smaller ISI, not in the CSI-2 receiver. The MIPI interface and driver are compatible across the entire i.MX8M family. Drivers are fully reusable; only DTS varies by board. Typical use-cases are low-power HMIs, compact cameras, and industrial modules (e.g., TechNexion, Variscite). Supports 4K30 / 1080p60 equivalent bandwidth, depending on sensor and ISI load.
