NXP i.MX8QM / QXP Series
The i.MX8QM and QXP feature advanced multi-pipeline routing and dual ISI support, making them suitable for automotive and high-end industrial applications. Our drivers fully support the complex routing and media-controller pipelines required for these processors.
NXP i.MX8QM
The i.MX8QM (Quad Max) features two Image Signal Processor (ISI) pipelines and up to two 4-lane MIPI CSI-2 receivers (not four). The “four CSI ports” sometimes referenced in older documents actually correspond to routing interfaces, not four independent full 4-lane MIPI PHYs.
- Two 4-lane MIPI CSI-2 receivers
- Dual Image Signal Processor (ISI)
- Multi-pipeline routing
- Automotive/Industrial grade
The CSI receiver block is based on the i.MX8QM MIPI-CSI2 bridge, similar to i.MX8M but extended for multi-pipeline routing. It uses the imx8-mipi-csi2 driver core and V4L2 async sub-devices. Device-tree defines the lane configuration, link-frequency (~800 MHz typical), hs-settle, and power regulators. Realistic operation supports two 4-lane sensors, not “4×4K60”. The dual ISI enables multi-pipeline processing but bandwidth is limited by the two MIPI PHYs. Builds use NXP BSP (L5.10/L5.15). Flashing is via U-Boot on the i.MX8QM MEK or custom automotive/industrial boards.
NXP i.MX8QXP
The i.MX8QXP shares a similar architecture to i.MX8QM, providing two 4-lane MIPI CSI-2 receivers, not four. It uses the same imx8-mipi-csi2 receiver + CSI bridge block and an identical register map and DTS layout.
- Two 4-lane MIPI CSI-2 receivers
- Shared architecture with i.MX8QM
- Identical register map / DTS layout
- Automotive-grade modules
V4L2 async sub-devices, media-controller routing, settle-time parameters, and power sequencing match i.MX8QM. Differences are mainly in clocking and domain isolation. It can support dual cameras, but not 4×4-lane simultaneous streams. Builds follow BSP L5.10/L5.15 or mainline. Popular on MEK and automotive-grade modules.
