TI Jacinto J721E / TDA4VM Series

High-Performance Camera Operation

The Jacinto J721E (TDA4VM) integrates Cadence CSI2RX + D-PHY IP, exposed as up to two CSI2RX capture instances (as per TI’s kernel documentation), each accepting 1–4 data-lanes per sensor. The driver (ti-j721e-csi2rx shim) wraps the CSI2RX bridge + D-PHY + DMA (SHIM) and integrates via V4L2 media controller API. Sensor drivers (I2C) register as async sub-devices; device-tree overlays define endpoint binding, lane-count, link-frequency, virtual channels if used, and power/reset regulators. The CSI2RX subsystem supports MIPI CSI v1.3, up to 16 virtual channels per input, and wire-rate up to 2.5 Gbps per lane (allowing 1–4-lane sensor connections). Recent upstream patches (2023–2025) enabled multi-stream (multi-DMA context/video-node) support, meaning multiple cameras (e.g. via serializers, FPDLink, or multiple CSI inputs) can be captured concurrently on compatible boards. Because camera pipeline configuration — sensor output format, link-lanes, PHY timing, board wiring, memory bandwidth — affects performance, the achievable resolution, frame-rate, and number of simultaneous cameras vary per board and sensor. TI provides examples (e.g. IMX219 modules, FPDLink fusion cameras) on SK/EVM or custom carriers via U-boot overlays. This makes J721E/TDA4VM a flexible platform for multi-camera, multi-stream, and ADAS/robotics-grade camera applications — but exact camera configurations must be validated per board/sensor combination.